Logic signal selection circuit

ABSTRACT

It is to achieve a logic signal selection circuit having high timing resolution and high speed. The logic signal selection circuit includes a current input type sense amplifier 320 which is provided with a threshold value which is an output of an equivalent center current generator 310 and positive logic input signals through transfer gates, a current input type sense amplifier 321 which is provided with a threshold value which is an output of an equivalent center current generator 311 and negative logic input signals through transfer gates, a differential amplifier 340 which receives and amplifies an output of the current input type sense amplifier 320 whose delay times are fine adjusted by a delay time adjuster 330, a differential amplifier 341 which receives and amplifies an output of the current input type sense amplifier 321 whose delay times are fine adjusted by a delay time adjuster 331, and a logic circuit 350 which receives both outputs of the differential amplifiers 340 and 341, and generates a logical sum of the both outputs. Because there is no voltage change in the input of the current input type sense amplifier, current flows will not occur to the capacitance C of the transfer gates which are in the OFF state and connected at the input of the current input type sense amplifier. Thus, it is able to output the selected input signal with high timing resolution and with high speed.

TECHNICAL FIELD

This invention relates to a logic signal selection circuit for selectinga high frequency logic signal and outputting the selected logic signalwith high timing resolution.

BACKGROUND ART

Because of the increasing operation speed in electric circuits, highertiming resolution is required in electric signals used in such electricapparatuses. In particular, a logic signal selection circuit whichselectively outputs a logic signal out of many logic signals is requiredto have a high timing resolution.

FIG. 7 shows an example of a logic signal selection circuit generallyused in the conventional technology. In this example, the number ofinput signals, which are negative logic, to an OR circuit is equal tothe number of input signals n to a NAND circuit.

FIG. 8(a) shows an example in which an OR circuit having n negativelogic inputs is formed of a CMOS circuit. In this circuit example, ngates which are N-channel MOS-FETs are connected in series while n gateswhich are P-channel MOSFETs are connected in parallel. As a consequence,a rising edge of an output signal waveform goes to a high level with arelatively short transition time, since one P-channel MOSFET driveswiring capacitance of the circuit and gate capacitance of the nextstage. However, a falling edge of the output signal waveform requires aconsiderably long time for going down to a low level as shown in FIG.8(b), since n stages of the N-channel MOSFETs drive the wiringcapacitance and the gate capacitance of the next stage. This is becausethe overall ON resistance is large by the series connection of the nMOSFETs.

FIG. 9 shows an example of a logic signal selection circuit usingtransfer gates. In this example, one transfer gate, which is ON, drivesthrough its ON resistance R, capacitance C of other n-1 transfer gateswhich are OFF. Therefore, rising and falling waveforms at a wired OR ofthe outputs of the transfer gates are affected by the capacitance C andthe resistance R. Thus, it is not proper to use this circuit examples asa signal selection circuit for high repetition frequency signals.

As in the foregoing, in the conventional logic signal selection circuit,high frequency signal selection is not attainable, since the wiringcapacitance, the gate capacitance of the next stage and the capacitanceof the transfer gates which are in the OFF state have to be charged bymeans of voltage changes.

Therefore, it is an object of the present invention to provide a logicsignal selection circuit which is capable of selecting a high frequencylogic signal with high timing resolution.

DISCLOSURE OF THE INVENTION

The structure of a logic signal selection circuit of the presentinvention includes a current input type sense amplifier 320 which isprovided with a threshold value which is an output of an equivalentcenter current generator 310 and positive logic input signals throughtransfer gates, a current input type sense amplifier 321 which isprovided with a threshold value which is an output of an equivalentcenter current generator 311 and negative logic input signals throughtransfer gates, a differential amplifier 340 which receives andamplifies an output of the current input type sense amplifier 320 whosedelay times are fine adjusted by a delay time adjuster 330, adifferential amplifier 341 which receives and amplifies an output of thecurrent input type sense amplifier 321 whose delay times are fineadjusted by a delay time adjuster 331, and a logic circuit 350 whichreceives both outputs of the differential amplifiers 340 and 341, andgenerates a logical sum of the both outputs.

Because there is no voltage change in the input of the current inputtype sense amplifier, current flows will not occur to the capacitance Cof the transfer gates which are in the OFF state and are connected atthe input of the current input type sense amplifier. Thus, it is able tooutput the selected input signal with high timing resolution and withhigh speed.

Further, by classifying the positive logic inputs and the negative logicinputs in separate groups, and providing such separately grouped inputsto the corresponding current input type sense amplifiers, delay timesfor the separate groups of input signals can be controlled independentlyfrom the other. Therefore, it is possible to output the selected inputsignal with high timing resolution and with a high speed without regardto the positive logic inputs or the negative logic inputs.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a circuit of an embodiment of thepresent invention.

FIG. 2 is a schematic circuit diagram of a current input type senseamplifier of the present invention.

FIG. 3 shows a schematic circuit diagram of another current input typesense amplifier of the present invention.

FIG. 4 is a block diagram of a timing signal generator using logicsignal selection circuit of the present invention.

FIG. 5 is a block diagram of the timing signal generator in whichpositive logic inputs and negative logic inputs are separately providedin accordance with the present invention.

FIG. 6 is a block diagram of the logic signal selection circuit in whichpositive logic inputs and negative logic inputs are separately providedin accordance with the present invention.

FIG. 7 is a circuit diagram showing a logic signal selection circuitgenerally used in the conventional technology.

FIG. 8 is a schematic circuit diagram showing n negative logic inputsCMOS OR circuit

FIG. 9 is a schematic diagram of a logic signal selection circuit usingtransfer gates.

BEST MODE FOR CARRYING OUT THE INVENTION

An embodiment of the present invention is explained in the following.

FIG. 1 shows a first embodiment of the present invention. This circuitis formed of an input signal selection circuit 10 which selects oneinput signal out of n input signals, and a current input type senseamplifier 20 which is connected to a wired OR. Since the input impedanceof the current input type sense amplifier 20 is almost zero, voltagechanges are not caused by input signals. As a result, a current flow toa stray capacitance C at an input point A will not occur, which meansthat the existence of the stray capacitance is negligible in thisexample.

In other words, a high speed logic signal selection circuit having hightiming resolution is achieved which has no delay times based on thecapacitance in the rising and falling edges of an input signal.

FIG. 2 shows examples of the current input type sense amplifier in whichFIG. 2(a) utilizes transistors, FIG. 2(b) utilizes MOSFETs, and FIG.2(c) utilizes differential amplifiers. In either circuit example, by theselected input signal, an input current to the current input type senseamplifier changes and a voltage output is obtained accordingly.

FIG. 3 shows an example of a current input type sense amplifier which isformed of CMOS transistors. Also in this example, an input current tothe current input type sense amplifier changes corresponding to theselected input signal, and a voltage output is obtained accordingly. Inthis circuit example, by regulating a current to a terminal I_(adj), athreshold current level with respect to the input current is determined.Thus, the delay time of logic signal can be freely regulated.

Further, in this example, it is also possible to delete the transistorsQ2 and Q9 and connect the transistors Q1 and Q8 directly to constantcurrent sources I₁ and I₂, respectively. In such a case, although aninput signal voltage varies, delay times in signal rising and fallingedges caused by the capacitance are small, since the input impedance issufficiently small.

Furthermore, in this example, it is also possible to form a currentinput type sense amplifier by inverting all the P-channels andN-channels of the FETs and voltage sources V_(DD) and V_(SS).

Other embodiments are explained in the following. FIG. 4 shows a secondembodiment of the present invention. This is a circuit block diagram ofa timing signal generation circuit having a logic signal selectioncircuit. The components in the block diagram of this circuit areclassified into the following blocks:

(1) Variable Delay Circuit 120

The variable delay circuit 120 includes m stages of variable delayelements 121 connected in series. In this case, m is a number of timingwhich divides one clock CLK period. The sum of all the delay times ofthe m stages of the variable delay elements 121 is controlled to beequal to one clock time by a feedback circuit 150.

(2) Phase Comparator 140

The phase comparator 140 is a circuit which outputs an electric currentor voltage signal proportional to a phase difference between signals e1and e2 supplied to two input terminals. A charge pump may be included inthe phase comparator 140. The signal e1 is an output of the last stageof the variable delay circuit 120 which is delayed by one clock periodfrom the clock signal CLK, and the signal e2 is the clock signal CLK.

(3) Feedback Circuit 150

The feedback circuit 150 is to determine a frequency characteristics ofa phase lock loop 100 formed of the variable delay circuit 120, thephase comparator 140 and the feedback circuit 150.

(4) Input Signal Selection Circuit 110

The input signal selection circuit 110 is to select one output signalout of m output signals from the variable delay elements 121 in thevariable delay circuit 120 to be generated as a timing signal through acurrent input type sense amplifier 20.

(6) Decoder 160

The decoder 160 generates a select signal based on the delay data forselecting one signal out of the m output signals from the variable delayelements 121 in the variable delay circuit 120.

In order to generate the fine delay time having a resolution of 1/m ofthe clock signal period, a phase lock loop circuit 100 controls thedelay times in the variable delay elements 121 in the variable circuit120 so that the delay time of one variable delay element is equal to 1/mof the period of the clock signal CLK. Therefore, an overall delay timeby the variable delay elements 121 is equal to one clock period of theclock CLK.

The outputs of the variable delay elements 121 of the variable delaycircuit 120 have the timing difference which is divided the clock CLK bym. One of these outputs is selected by the input signal selectioncircuit 110 and is input to the current input type sense amplifierwhereby converted to a voltage signal and output therefrom. The timingsignals obtained by the outputs of the variable delay elements have hightiming accuracy and thus, the timing signal generation circuit of thisembodiment having the input signal selection circuit and the currentinput type sense amplifier 20 can accomplish sufficient timingresolution.

Another embodiment of the present invention is explained in thefollowing.

In case where inverters are employed as variable delay elements 221, atiming signal generation circuit is configured as shown in FIG. 5. Inthis situation, signals to be selected alternately show positive logicor negative logic at the output of the inverters and are input to aninput signal selection circuit 210. To maintain the high timingresolution with a high operation speed, the positive logic input signalsand the negative logic input signals are grouped and provided tocorresponding current input type sense amplifiers separately providedwith each other. The outputs of the logic in both sense amplifiers areadjusted by differential amplifiers.

FIG. 6 is a block diagram showing an example of a logic signal selectioncircuit in which input signals are separated to a positive logic inputsignal group and a negative logic input signal group. This circuitexample has a current input type sense amplifier 320 which is providedwith a threshold value which is an output of an equivalent centercurrent generator 310 and positive logic input signals through transfergates, a current input type sense amplifier 321 which is provided with athreshold value which is an output of an equivalent center currentgenerator 311 and negative logic input signals through transfer gates, adifferential amplifier 340 which receives and amplifies an output of thecurrent input type sense amplifier 320 whose delay times are fineadjusted by a delay time adjuster 330, a differential amplifier 341which receives and amplifies an output of the current input type senseamplifier 321 whose delay times are fine adjusted by a delay timeadjuster 331, and a logic circuit 350 which receives both outputs of thedifferential amplifiers 340 and 341, and generates a logical sum of theboth outputs.

INDUSTRIAL APPLICABILITY

Since it is configured as described in the foregoing, the presentinvention has the following effects.

Because there is no voltage change in the input of the current inputtype sense amplifier, current flows will not occur to the capacitance Cof the transfer gates which are in the OFF state and are connected atthe input of the current input type sense amplifier. Thus, it is able tooutput the selected input signal with high timing resolution and with ahigh speed.

Further, by classifying the positive logic inputs and the negative logicinputs in separate groups, and providing such separately grouped inputsto the corresponding current input type sense amplifiers, delay timesfor the separate groups of input signals can be controlled independentlyfrom the other. Therefore, it is possible to output the selected inputsignal with high timing resolution and with a high speed without regardto the positive logic inputs or the negative logic inputs.

The above noted features of the present invention are especially usefulfor timing signal generation circuits which need to have high timingresolution.

What is claimed is:
 1. A logic signal selection circuit comprising:afirst current input type sense amplifier (320) which is provided with afirst threshold value which is an output of a first equivalent centercurrent generator (310) and positive logic input signals throughtransfer gates; a second current input type sense amplifier (321) whichis provided with a second threshold value which is an output of a secondequivalent center current generator (311) and negative logic inputsignals through transfer gates; a first differential amplifier (340)which receives and amplifies an output of the first current input typesense amplifier (320) whose delay times are fine adjusted by a firstdelay time adjuster (330); a second differential amplifier (341) whichreceives and amplifies an output of the second current input type senseamplifier (321) whose delay times are fine adjusted by a second delaytime adjuster (331); and a logic circuit (350) which receives bothoutputs of the first and second differential amplifiers (340, 341), andgenerates an output signal which is a logical sum of the both outputs.2. A logic signal selection circuit for selecting a logic signal from aplurality of logic signals, comprising:a plurality of transfer gatescorresponding to the plurality of logic signals, an input of each of thetransfer gates receives one of the plurality of logic signals and anoutput of each of the transfer gates is connected with one another in awired OR fashion; and a current sense amplifier which has an inputresistance smaller than an ON resistance of each of the transfer gates,the current sense amplifier converting an input current received from anoutput of the wired OR of the transfers gate into a voltage proportionalto the current.
 3. A logic signal selection circuit as defined in claim2, wherein each of the transfer gates is a CMOS transfer gate havinginput and output terminals for the logic signal passing therebetween anda select terminal for receiving a selection signal to ON/OFF control thetransfer gate.
 4. A logic signal selection circuit as defined in claim2, wherein the current sense amplifier is connfigured by a tansistorwhich forms a common base amplifier wherein a base of the transistor isconnected to the ground and the input current from the transfer gate isreceived by an emitter of the transistor while an output voltageproportional to the input current is produced at a collector of thetransistor.
 5. A logic signal selection circuit as defined in claim 2,wherein the current sense amplifier is configured by a MOS field effecttransistor (MOSFET) which forms a common gate amplifier wherein a gateof the MOSFET is connected to the ground and the input current from thetransfer gate is received by a source of the MOSFET while an outputvoltage proportional to the input current is produced at a drain of theMOSFET.
 6. A logic signal selection circuit as defined in claim 2,wherein the current sense amplifier is configured by a differentialamplifier having a negative feedback loop wherein the input current fromthe transfer gate is received by an inverting input terminal of thedifferential amplifier while a non-inverting input terminal of thedifferential amplifier is connected to the ground.
 7. A logic signalselection circuit, comprising:a plurality of variable delay devicesserially connected with one another, each variable delay device having apropagation time delay which is substantially smaller than one period ofa clock signal; a phase comparator which compares a total delay time ofthe plurality of variable delay devices derived from the last stage ofthe variable delay devices with the clock signal and generates a voltagesignal representing a time difference between the two; a feedbackcircuit which returns the voltage signal from the phase comparator tothe variable delay devices to form a phase locked loop so that the totaldelay time of the variable delay devices is regulated to be equal to theone period of the clock signal; a plurality of transfer gatescorresponding to the plurality of the delay devices; an input of each ofthe transfer gates receiving an output current of corresponding one ofthe delay devices and an output of each of the transfer gates beingconnected with one another in a wired OR fashion; one of the transfergates being selected to transfer the output current from one of thedelay devices to the wired OR; and a current sense amplifier which hasan input resistance smaller than an ON resistance of each of thetransfer gates, the current sense amplifier converting the outputcurrent of the delay device received from the wired OR into a voltageproportional to the input current.
 8. A logic signal selection circuitas defined in claim 7, wherein each of the transfer gates is a CMOStransfer gate having input and output terminals for the output currentof the delay device passing therebetween and a select terminal forreceiving a selection signal to ON/OFF control the transfer gate.
 9. Alogic signal selection circuit as defined in claim 7, wherein thecurrent sense amplifier is configured by a transistor which forms acommon base amplifier wherein a base of the transistor is connected tothe ground and the output current from the transfer gate is received byan emitter of the transistor while an output voltage proportional to theoutput current is produced at a collector of the transistor.
 10. A logicsignal selection circuit as defined in claim 7, wherein the currentsense amplifier is configured by a MOS field effect transistor (MOSFET)which forms a common gate amplifier wherein a gate of the MOSFET isconnected to the ground and the output current from the transfer gate isreceived by a source of the MOSFET while an output voltage proportionalto the output current is produced at a drain of the MOSFET.
 11. A logicsignal selection circuit as defined in claim 7, wherein the currentsense amplifier is configured by a differential amplifier having anegative feedback loop wherein the output current from the transfer gateis received by an inverting input terminal of the differential amplifierwhile a non-inverting input terminal of the differential amplifier isconnected to the ground.
 12. A logic signal selection circuit,comprising:a plurality of variable delay devices serially connected oneanother, each variable delay device having a propagation time delaywhich is substantially smaller than one period of a clock signal; aphase comparator which compares a total delay time of the plurality ofvariable delay devices derived from the last stage of the variable delaydevices with the clock signal and generates a voltage signalrepresenting a time difference between the two; a feedback circuit whichreturns the voltage signal from the phase comparator to the variabledelay devices to form a phase locked loop so that the total delay timeof the variable delay devices is regulated to be equal to the one periodof said clock signal; a first group of transfer gates for receivingoutput currents of a first group of the variable delay devices, anoutput of each of the first group of the transfer gates being connectedwith one another to form a first wired OR; one of the first group of thetransfer gates being selected to transfer the output current from one ofthe first group of the delay devices to the first wired OR; a secondgroup of transfer gates for receiving output currents of a second groupof the variable delay devices, an output of each of the second group ofthe transfer gates being connected with one another to form a secondwired OR; one of the second group of the transfer gates being selectedto transfer the output current from one of the second group of the delaydevices to the second wired OR; a first current sense amplifier forconverting the output current of one of the first group of the delaydevices received from the first wired OR into a first voltageproportional to the output current; a second current sense amplifier forconverting the output current of one of the second group of the delaydevices received from the second wired OR into a second voltageproportional to the output current; and an OR gate for receiving thefirst voltage from the first current sense amplifier and the secondvoltage from the second current sense amplifier and producing either ofthe voltages at an output terminal.
 13. A logic signal selection circuitas defined in claim 12, wherein an output of each of the first group ofthe delay devices produces a positive logic signal and an output of eachof the second group of the delay devices produces a negative logicsignal.
 14. A logic signal selection circuit as defined in claim 12,wherein each of the first and second groups of the transfer gates is aCMOS transfer gate having input and output terminals for the outputcurrent of the delay device passing therebetween and a select terminalfor receiving a selection signal to ON/OFF control the transfer gate.15. A logic signal selection circuit as defined in claim 12, whereineach of the first and second current sense amplifiers is configured by atransistor which forms a common base amplifier wherein a base of thetransistor is connected to the ground and the output current from thetransfer gate is received by an emitter of the transistor while anoutput voltage proportional to the output current is produced at acollector of the transistor.
 16. A logic signal selection circuit asdefined in claim 12, wherein each of the first and second current senseamplifiers is configured by a MOS field effect transistor (MOSFET) whichforms a common gate amplifier wherein a gate of the MOSFET is connectedto the ground and the output current from the transfer gate is receivedby a source of the MOSFET while an output voltage proportional to theoutput current is produced at a drain of the MOSFET.
 17. A logic signalselection circuit as defined in claim 12, wherein each of the first andsecond current sense amplifiers is configured by a differentialamplifier having a negative feedback loop wherein the output currentfrom the transfer gate is received by an inverting input terminal of thedifferential amplifier while a non-inverting input terminal of thedifferential amplifier is connected to the ground.